1. Field of the Invention
This invention relates generally to hardware design for high density logic circuits and has particular application to code testing in design development, and enhancements thereto.
2. Background
Code coverage is a compute intense activity involved in hardware emulation used in the hardware design process. A fair background description can be found at http://www.bullseye.com/coverage.html. A great deal of expense and time can be saved with improvements and enhancements to basic code coverage tools.
Specifically, if one can identify specific functional parts of a circuit design, one can direct the emulation of those parts with specificity to ensure adequate code coverage can be accomplished. This is particularly useful where a functional circuit's truth table is complex, and time to emulate for each possible combination is an important consideration. Also, determining which logic gates are unexercised in an emulation is essential to knowing whether the design is adequately tested. The two ideas presented in this patent are directed to these goals.
It is helpful to have some background terms defined.
The most basic is HDL or Hardware Description Language. The most common HDLs in use today are Verilog and VHDL (which stands for VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit). They describe circuit designs in a technology-independent manner using a high level of abstraction.
A netlist is the HDL description of the hardware design. The netlist includes information on a target technology for the design, but not the physical design. A (usually) separate physical design team will place and route signal paths and get the design to meet the timing requirements of the functionality.
Coverage probes are logical flags placed into the HDL or VHDL where something is happening of interest. If one is “instrumenting” the coverage probes, that means inserting extra VHDL statements that will appear in the instrumented VHDL output file (so the coverage tools have access or hooks into the probes to use them as may be desired.) Because a probe looks like a circuit, it is given a hierarchical name so that it can be found and not confused with any other circuit in the design.
It is also useful to realize that naming conventions are important for finding logic in a large VHDL or Verilog file. Typically there is a hierarchical convention used, where a piece of logic, say, Register W fits within a subset of logic called for example, C within a part of a high level function, say, B, which in turn fits within a larger contextual piece of logic performing that high level function A, and which in turn fits within an even larger contextual piece of an even higher level function, for example, bus controller BC. Thus, the identification of Register W would be “BC:A:B:C:RegisterW.” Other naming conventions can be used but generally a hierarchical approach is taken due to its simplicity.
It is also useful to recognize the difference between emulation and simulation, which those who work in these areas assume. Simulation is done in fairly small segments of logic, compared to emulation, and does not require many real-world attributes. An example of Emulation may be that of a software emulation of a testbench for running an entire device (ASIC, or ASIC with components on a circuit board) to determine if it has any faults. At speed testing, real-world device attributes and the like are included in the emulation run, whereas a simulator need only test the functionality of the logic design, and generally works for earlier phases of the design process.
Finally, the term reset trigger has a known meaning. We generally use it in this patent with the meaning it has as something that will reset values of coverage flip-flops to a known state. It is called a “trigger” because it triggers sensitivity lists to capture initial values.